Computational Models for Intelligence and Automation
A Comparative Study of Different 7T SRAM Cells Enhancing the Throughput for Low Power Operations
Authors: Anshumat Dinesh, Yogita Chopra and Poornima Mittal
Publishing Date: 28-08-2025
ISBN: 978-81-975670-1-8
Abstract
This paper presents a comprehensive comparative analysis of three 7T SRAM cell designs at the 32nm technology node with a supply voltage of 1.2V, evaluating Static Noise Margins, Write Time, Current Ratio, and Power Consumption through SPICE simulations. While sharing a common memory core, the designs feature distinct port configurations that significantly impact performance. The single-port, single-ended 7T-1 demonstrates superior HSNM (436 mV) and read power efficiency, while the Schmitt trigger-based 7T-3 achieves the highest write margin (599 mV), lowest write/hold power, and fastest write operation (0.1 ns critical write time). All designs show similar current ratios, with 7T-1 and 7T-3 exhibiting approximately double the ratio of 7T-2. Our analysis reveals fundamental trade-offs: 7T-2 offers the best overall stability balance, 7T-1 excels in power-sensitive applications despite modest write margin reduction, and 7T-3 provides exceptional write performance at the cost of read/hold stability. These findings provide critical insights for SRAM design optimization in low-power applications, particularly for IoT and portable computing devices.
Keywords
SRAM, HSNM, RSNM, Dynamic power, static power, 7T
Cite as
Anshumat Dinesh, Yogita Chopra and Poornima Mittal, "A Comparative Study of Different 7T SRAM Cells Enhancing the Throughput for Low Power Operations", In: Puneet Kumar Gupta (eds), Computational Models for Intelligence and Automation, SCRS, India, 2025, pp. 14-22. https://doi.org/10.56155/978-81-975670-1-8-2