Next-Gen Data Analytics and Intelligent Automation
A Fully-Differential-Double-FoldedCascode-Push-Pull OTA with 151 dB CMRR
Authors: Sumit Kumar and R. K Sharma
Publishing Date: 24-12-2025
ISBN: 978-81-975670-6-3
Abstract
A fully-differential-double-folded-cascode-push-pull(FDDFCPP) OTA is presented. The OTA is optimized for large values of the power-supply-rejection-ratio(PSRR) and common-mode-rejection-ratio(CMRR). The FDDFCPP OTA consists of a fullydifferential-folded cascode as the first stage, which provides a large signal swing and high DC gain. The 2nd stage of the proposed OTA is a push-pull amplifier stage, which improves the transient behavior of the proposed OTA. The proposed circuit is frequency compensated using Miller compensation. The proposed design is simulated using an Electric-VLSI tool with an LTspice simulator using 180nm CMOS technology. The proposed OTA provides a CMRR of 151.4dB(DC), PSRR of 52.40dB(DC), unity-gain-frequency(UGF) of 37.15MHz with DC gain of 32.5dB, phase-margin of 56.57() and power consumption of 0.52mW with capacitive load of 3pF.
Keywords
Folded-cascode, Push-pull, CMRR, PSRR
Cite as
Sumit Kumar and R. K Sharma, "A Fully-Differential-Double-FoldedCascode-Push-Pull OTA with 151 dB CMRR", In: Kusum Kumari Bharti and Noor Firdoos Jahan (eds), Next-Gen Data Analytics and Intelligent Automation, SCRS, India, 2025, pp. 11-22. https://doi.org/10.56155/978-81-975670-6-3-2