Advancements in Communication and Systems
Fast Inverse Square Root using FPGA
Authors: Abhay Chopde, Sharvari Bodas, Varada Deshmukh and Shamish Bramhekar
Publishing Date: 12-02-2024
ISBN: 978-81-955020-7-3
Abstract
The Fast Inverse Square Root (FISR) algorithm, originally introduced in the Quake III source code, accomplishes the vector normalization task required in graphics application through basic multiplication and bit-shifting operations. The core of this algorithm relies on the use of approximation techniques to enhance an initial estimation, which is primarily based on a designated “magic” constant. The implemented Verilog code utilizes the Newton-Raphson iterations, modified booth’s multiplier, and the inverse square root, featuring a core “Inverse Square Root” module with 32-bit input and output. This paper makes use of two magic constants “0x5f3e34bc” and “0x5f3759df” aiming to improve the accuracy. It selects a magic constant based on the exponent bit. The approximation occurs through two Newton-Raphson iterations. A Booth Multiplier is used, that is using a Radix-4 encoding scheme to reduce partial product generation, making it faster.
Keywords
FPGA, Fast inverse square root, Radix 4 Booth’s multiplier.
Cite as
Abhay Chopde, Sharvari Bodas, Varada Deshmukh and Shamish Bramhekar, "Fast Inverse Square Root using FPGA", In: Ashish Kumar Tripathi and Vivek Shrivastava (eds), Advancements in Communication and Systems, SCRS, India, 2024, pp. 231-239. https://doi.org/10.56155/978-81-955020-7-3-21