Computational Models for Intelligence and Automation
Layered Transaction-Level Verification of a Cache Controller for Enhanced Performance and Reusability
Authors: Sowmya K B, Aditya Varma, Meghana P Manru, Santhosh V and Syed Abdur Rahman
Publishing Date: 28-08-2025
ISBN: 978-81-975670-1-8
Abstract
This paper focuses on developing a comprehensive testbench for a cache controller, structured to simplify complexity while adhering to Universal Verification Methodology (UVM) principles. The cache controller is responsible for managing load/store operations, handling cache hits and misses, and coordinating data transfers with an L2 cache. The design incorporates a finite state machine (FSM) with states like Idle, CompareTag, WriteBuffer, and Allocate to efficiently manage cache operations and data handling.The verification framework is built using transaction-level modeling in SystemVerilog and integrates components such as agents, drivers, monitors, generators, and scoreboards. These components work together to simulate various cache operations, validate the controller’s behavior, and ensure robustness under different conditions. By generating randomized transactions and comparing expected outcomes with actual results using a scoreboard, the framework identifies errors and ensures design accuracy. The environment achieves 100% assertion and reduces verification time by 25% compared to traditional methods. The integration of assertions and functional coverage ensures a thorough verification process, while the modular design makes the framework reusable and scalable for other applications. This approach provides a streamlined and effective solution for validating cache controller designs.
Keywords
UVM-like testbench; cache controller; cache hit/miss; L2 cache; SystemVerilog; verification environment; FSM.
Cite as
Sowmya K B, Aditya Varma, Meghana P Manru, Santhosh V and Syed Abdur Rahman, "Layered Transaction-Level Verification of a Cache Controller for Enhanced Performance and Reusability", In: Puneet Kumar Gupta (eds), Computational Models for Intelligence and Automation, SCRS, India, 2025, pp. 59-69. https://doi.org/10.56155/978-81-975670-1-8-6